MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units
By: Sebastian Billaudelle , Laura Kriener , Filippo Moro and more
Potential Business Impact:
Makes tiny computers remember more with less power.
Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes. We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model.
Similar Papers
A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
Hardware Architecture
Makes AI chips faster and use less power.
Minion Gated Recurrent Unit for Continual Learning
Machine Learning (CS)
Makes smart computer programs run faster, smaller.
In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning
Machine Learning (CS)
Trains AI better with cheaper, simpler computer parts.