4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation
By: Fuyuki Kihara , Seiji Uenohara , Satoshi Awamura and more
Potential Business Impact:
Makes AI faster and uses less power.
Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells.
Similar Papers
NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
Hardware Architecture
Makes computer chips do math inside their memory.
TReCiM: Lower Power and Temperature-Resilient Multibit 2FeFET-1T Compute-in-Memory Design
Emerging Technologies
Makes AI chips work better in different temperatures.
An RRAM compute-in-memory architecture for high energy-efficient processing of binary matrix-vector multiplication in cryptography
Emerging Technologies
Makes computers faster and use less power.