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FTI-TMR: A Fault Tolerance and Isolation Algorithm for Interconnected Multicore Systems

Published: October 19, 2025 | arXiv ID: 2510.16896v1

By: Yiming Hu

Potential Business Impact:

Keeps computers working even when parts break.

Business Areas:
Hardware Hardware

Two-Phase Triple Modular Redundancy TMR divides redundancy operations into two stages, omitting part of the computation during fault-free operation to reduce energy consumption. However, it becomes ineffective under permanent faults, limiting its reliability in critical systems. To address this, Reactive-TMR (R-TMR) introduces permanent fault isolation mechanisms for faulty cores, tolerating both transient and permanent faults. Yet, its reliance on additional hardware increases system complexity and reduces fault tolerance when multiple cores or auxiliary modules fail. This paper proposes an integrated fault-tolerant architecture for interconnected multicore systems. By constructing a stability metric to identify reliable machines and performing periodic diagnostics, the method enables permanent fault isolation and adaptive task scheduling without extra hardware. Experimental results show that it reduces task workload by approximately 30% compared to baseline TMR and achieves superior fault coverage and isolation accuracy, significantly improving both reliability and energy efficiency.

Page Count
11 pages

Category
Computer Science:
Distributed, Parallel, and Cluster Computing