Assessing Large Language Models in Generating RTL Design Specifications
By: Hung-Ming Huang , Yu-Hsin Yang , Fu-Chieh Chang and more
Potential Business Impact:
Helps computers understand computer chip plans automatically.
As IC design grows more complex, automating comprehension and documentation of RTL code has become increasingly important. Engineers currently should manually interpret existing RTL code and write specifications, a slow and error-prone process. Although LLMs have been studied for generating RTL from specifications, automated specification generation remains underexplored, largely due to the lack of reliable evaluation methods. To address this gap, we investigate how prompting strategies affect RTL-to-specification quality and introduce metrics for faithfully evaluating generated specs. We also benchmark open-source and commercial LLMs, providing a foundation for more automated and efficient specification workflows in IC design.
Similar Papers
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
Hardware Architecture
AI writes computer chip instructions automatically.
ML For Hardware Design Interpretability: Challenges and Opportunities
Machine Learning (CS)
Helps computers design faster chips for AI.
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
Hardware Architecture
Helps engineers understand computer chip code better.